Analog-digital conversion apparatus and digital-analog conversion apparatus

ABSTRACT

An analog-digital conversion apparatus has a jitter detecting circuit for detecting the amount of jitter included in a sampling clock generated, and a jitter applying circuit for providing an analog signal to be subjected to the analog-digital conversion with a delay based on the amount of jitter detected to prevent phase shift of the sampling due to jitter of the sampling clock in the analog-digital converter.

This application is a 371 of PCT/JP2005/010372 filed on Jun. 6, 2005.

TECHNICAL FIELD

The present invention relates to an analog-digital conversion apparatusand a digital-analog conversion apparatus capable of reducingdeterioration in conversion accuracy.

BACKGROUND ART

It is known in an analog-digital conversion apparatus that jitterincluded in an input sampling clock will vary the sampling phase of thesignal to be converted and deteriorate conversion accuracy. To suppressthe deterioration in conversion accuracy due to jitter, a method isgenerally employed which uses an oscillator with low jitter to generatethe sampling clock. In addition, Patent Document 1, for example,proposes a method of correcting the deterioration due to jitter afterconverting a signal to be converted to a digital signal.

On the other hand, the same deterioration in conversion accuracy due tojitter occurs in a digital-analog conversion apparatus as well. Withthis apparatus, the period over which the analog value is maintained ata fixed value is identical to the period of the sampling clock. Thus,the period over which the analog value is maintained at a fixed valuefluctuates owing to jitter, and spurious frequency components aresuperimposed, thereby deteriorating the conversion accuracy. In thiscase also, to reduce the deterioration in conversion accuracy, a methodis generally employed which uses an oscillator with low jitter togenerate the sampling clock.

Patent Document 1: Japanese patent laid-open No. 4-150354/1992.

Although the conventional analog-digital conversion apparatus anddigital-analog conversion apparatus employ the foregoing methods toreduce the deterioration in conversion accuracy, they have a problem ofincreasing cost because of the high accuracy required when using theoscillator with low jitter. In addition, the method described in PatentDocument 1 has a problem of requiring a configuration for carrying outcomplicated digital processing to correct the deterioration inconversion accuracy.

The present invention is implemented to solve the foregoing problems.Therefore it is an object of the present invention to provide ananalog-digital conversion apparatus and a digital-analog conversionapparatus capable of preventing the deterioration in the conversionaccuracy even if the sampling clock includes jitter.

DISCLOSURE OF THE INVENTION

An analog-digital conversion apparatus in accordance with the presentinvention includes: an analog-digital converter for carrying outanalog-digital conversion of an analog signal; an oscillator forgenerating a sampling clock used for sampling the analog signal by theanalog-digital converter; a jitter detecting circuit for detecting theamount of jitter included in the sampling clock generated; and a jitterapplying circuit for providing the analog signal to be subjected to theanalog-digital conversion with a delay based on the amount of jitterdetected to prevent phase shift of the sampling due to jitter of thesampling clock in the analog-digital converter.

In this way, it offers an advantage of being able to compensate for thedistortion due to the jitter in the sampling by shifting the phase ofthe analog signal to be subjected to the analog-digital conversionbefore the conversion in accordance with the amount of jitter of thesampling clock. As a result, it can obtain substantially the samesampled values as in the ideal conditions in which the jitter of thesampling clock is not present, thereby offering an advantage of beingable to implement highly accurate analog-digital conversion.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of an analog-digitalconversion apparatus of an embodiment 1 in accordance with the presentinvention;

FIG. 2 is a block diagram showing a configuration of a jitter detectingcircuit of the embodiment 1 in accordance with the present invention;

FIG. 3 is a time chart illustrating an output example of the jitterdetecting circuit of the embodiment 1 in accordance with the presentinvention;

FIG. 4 is a block diagram showing a configuration of a jitter applyingcircuit of the embodiment 1 in accordance with the present invention;

FIG. 5 is a diagram illustrating sampling operation of an ideal samplingclock;

FIG. 6 is a diagram illustrating conventional sampling operation basedon a sampling clock including jitter;

FIG. 7 is a diagram illustrating sampling operation based on a samplingclock including jitter of the embodiment 1 in accordance with thepresent invention;

FIG. 8 is a block diagram showing a configuration of the analog-digitalconversion apparatus of an embodiment 2 in accordance with the presentinvention;

FIG. 9 is a block diagram showing a configuration of a digital-analogconversion apparatus of an embodiment 3 in accordance with the presentinvention;

FIG. 10 is a block diagram showing a configuration of a jitter applyingcircuit of the embodiment 3 in accordance with the present invention;

FIG. 11 is a diagram illustrating digital-analog conversion operationdue to an ideal sampling clock;

FIG. 12 is a diagram illustrating conventional digital-analog conversionoperation based on a sampling clock including jitter;

FIG. 13 is a diagram illustrating correction operation afterdigital-analog conversion based on a sampling clock including jitter ofthe embodiment 3 in accordance with the present invention; and

FIG. 14 is a block diagram showing a configuration of the digital-analogconversion apparatus of an embodiment 4 in accordance with the presentinvention.

BEST MODE FOR CARRYING OUT THE INVENTION

The best mode for carrying out the invention will now be described withreference to the accompanying drawings to explain the present inventionin more detail.

EMBODIMENT 1

FIG. 1 is a block diagram showing a configuration of the analog-digitalconversion apparatus of an embodiment 1 in accordance with the presentinvention.

In FIG. 1, an oscillator 10, which is an oscillator for generating asampling clock, has a possibility that the sampling clock includes ajitter component. The output sampling clock is supplied to a jitterdetecting circuit 20 and an analog-digital converter 40. The jitterdetecting circuit 20 detects the amount of jitter included in thesampling clock generated by the oscillator 10, and supplies it to ajitter applying circuit 30. The jitter applying circuit 30 carries outphase shift processing by providing a delay based on the amount ofjitter detected by the jitter detecting circuit 20 to the analog signalto be subjected to the analog-digital conversion by the analog-digitalconverter 40. The analog-digital converter 40 converts the analog signalto be subjected to the analog-digital conversion, which passes throughthe phase shift processing based on the delay, to a digital signal. Adelay element 60 provides the sampling clock input to the analog-digitalconverter 40 with a delay equal to the processing time of the jitterdetecting circuit 20 and jitter applying circuit 30.

The jitter detecting circuit 20 has a configuration as shown in FIG. 2,for example. A frequency-voltage converter circuit 25 converts, whensupplied with the sampling clock generated by the oscillator 10, thefrequency of the sampling clock to a voltage signal. The voltage signalconverted undergoes subtraction processing by a subtracter 26 thatsubtracts a reference voltage 27 from the voltage signal, and becomes avoltage signal representing only frequency fluctuation. Here, considerthe case where it is assumed that the frequency of the sampling clock ofthe oscillator 10 is 30.72 MHz, and the frequency fluctuates about thatfrequency (30.72 MHz) because of jitter. When the reference voltage 27is the voltage corresponding to 30.72 MHz passing through thefrequency-voltage conversion, the detection voltage (the amount ofjitter) output from the jitter detecting circuit 20 becomes a voltagefluctuating about zero volt in response to fluctuations in the frequencydue to the jitter. FIG. 3 illustrates an example of the amount of jitterdetected by the jitter detecting circuit 20. The horizontal axis is atime axis, and the vertical axis represents the amount of jitter interms of frequency fluctuation Δf.

The jitter applying circuit 30 has a configuration as shown in FIG. 4. Atap selecting section 31, receiving the frequency fluctuation A f whichis detected by the jitter detecting circuit 20 and represents the amountof jitter, compares them with a predetermined reference voltage (such as−B, −A, 0, A, B). The frequency fluctuation Δf is replaced by a tapselection signal according to the large and small relationships with thereference voltage, and the tap selection signal is supplied to a tapswitching section 32. On the other hand, the analog signal to besubjected to the analog-digital conversion is supplied to a first end ofthe series connection of a plurality of delay elements 33, and isprovided with the delay as follows. When the number of the delayelements 33 connected in series is assumed to be four as shown in FIG. 4(actually the number is great), the delay output can be pulled out ofeach of the four output terminals of the delay elements. Each outputterminal of the delay elements 33 is connected to a corresponding tap ofthe tap switching section 32. Each tap is selected in response to thetap selection signal, and the signal obtained from the tap selectedbecomes the analog signal to be subjected to the analog-digitalconversion, to which the delay corresponding to the frequencyfluctuation Δf is provided. Thus, the analog signal to be subjected tothe analog-digital conversion passes through the phase shift processingaccording to the amount of jitter detected.

Next, the details of the sampling operation when employing theanalog-digital conversion apparatus of FIG. 1 will be described.

If an ideal sampling clock without any jitter component is used, theanalog signal to be subjected to the analog-digital conversion is freefrom phase fluctuations as illustrated in FIG. 5. Thus, it is sampled atregular intervals. In practice, however, the sampling clock deliveredfrom the oscillator 10 is apt to include the jitter component.Accordingly, when only the analog-digital converter 40 is used, theanalog signal to be subjected to the analog-digital conversion issampled by the sampling clock including the jitter component, andbecomes as illustrated in FIG. 6. More specifically, since the samplingclock varies its sampling phases from its original value due to thejitter, the sampling values differ from those of FIG. 5, therebydeteriorating the conversion accuracy by these amounts. In contrast withthis, when the analog-digital conversion apparatus in accordance withthe present invention is applied, the analog-digital conversion iscarried out after the analog signal to be subjected to theanalog-digital conversion is provided with the delay corresponding tothe amount of jitter detected as illustrated in FIG. 7. Thus, thedeterioration in conversion accuracy due to jitter can be compensated.The compensation is carried out by the jitter applying circuit 30 byadding the delay corresponding to the amount of jitter detected to theanalog signal to be subjected to the analog-digital conversion. As aresult, the sampled values obtained by the analog-digital conversionbecome substantially equal to the values in the ideal state withoutjitter.

As described above, the present embodiment 1 is configured in such amanner that the jitter detecting circuit detects the amount of jitterincluded in the sampling clock, and the jitter applying circuit providesthe delay based on the amount of jitter detected to the analog signal tobe subjected to the analog-digital conversion, thereby preventing thephase shift of the sampling in the analog-digital converter due to thejitter of the sampling clock. Thus, the present embodiment 1 can obtainsubstantially the same sampled values as in the ideal condition withoutjitter, thereby being able to implement the highly accurateanalog-digital conversion.

EMBODIMENT 2

The foregoing embodiment 1 is described by way of example ofoversampling in which the frequency band of the analog signal to besubjected to the analog-digital conversion is equal to or less than halfthe frequency of the sampling clock. The present embodiment 2 will bedescribed by way of example of the analog-digital conversion apparatusthat carries out undersampling.

Assume here that the frequency of the sampling clock is fs, the minimumfrequency in the frequency band of the analog signal to be subjected tothe analog-digital conversion is fmin, and the maximum frequency isfmax. When sampling the signal in the conditions ofN×fs≦fmin and fmax≦(N+1)×fs  (1)by the sampling clock frequency fs, the fluctuations in the sampledphases involved in the jitter of the sampling clock as shown in FIG. 6increase by a factor of N. FIG. 8 is a block diagram showing aconfiguration of the analog-digital conversion apparatus of theembodiment 2 in accordance with the present invention, which considersthe case of undersampling.

In FIG. 8, the same components as those of FIG. 1 are designated by thesame reference numerals and their description will be omitted inprinciple. The configuration includes in addition to that of FIG. 1 ajitter multiplication circuit 50 and a variable DC voltage source 55.

The jitter multiplication circuit 50 is a circuit for multiplying theamount of jitter, the output of the jitter detecting circuit 20, by N.The value N is made variable by a control signal output from thevariable DC voltage source 55. The amount of jitter multiplied by thejitter multiplication circuit 50 is supplied to the jitter applyingcircuit 30. The jitter applying circuit 30 adds to the analog signal tobe subjected to the analog-digital conversion a delay that will providethe phase shift of N times, and outputs.

As described above, the embodiment 2 is configured in such a manner thatthe jitter amount multiplication circuit multiplies the amount of jitterdetected by the jitter detecting circuit, and the jitter applyingcircuit provides the analog signal to be subjected to the analog-digitalconversion with the delay based on the amount of jitter multiplied.Thus, the analog-digital converter can obtain substantially the samesampled values as those in the ideal condition without jitter, therebybeing able to implement the highly accurate analog-digital conversionfor the undersampling.

EMBODIMENT 3

FIG. 9 is a block diagram showing a configuration of the digital-analogconversion apparatus of an embodiment 3 in accordance with the presentinvention.

In FIG. 9, an oscillator 210, which is an oscillator for generating asampling clock, has a possibility that the sampling clock includes ajitter component. The sampling clock generated is supplied to a jitterdetecting circuit 220 and a digital-analog converter 240. The jitterdetecting circuit 220 detects the amount of jitter included in thesampling clock generated by the oscillator 210, and supplies it to ajitter applying circuit 230. The jitter applying circuit 230 carries outphase shift processing for the signal converted by the digital-analogconverter 240 according to the delay based on the amount of jitterdetected by the jitter detecting circuit 220. The digital-analogconverter 240 carries out digital-analog conversion of the input digitalsignal to be converted in synchronism with the sampling clock. A delayelement 260 provides the signal passing through the digital-analogconversion with a delay equal to the processing time of the jitterdetecting circuit 220, and supplies to the jitter applying circuit 230.

As the jitter detecting circuit 220, a circuit with the sameconfiguration as the circuit 20 shown in FIG. 2 can be employed. Inaddition, as for the configuration of the jitter applying circuit 230, acircuit with the same configuration as the circuit 30 shown in FIG. 4can be used. As for its operation, however, since the signal to besubjected to the phase shift processing is the signal passing throughthe digital-analog conversion, its operation will be described withreference to FIG. 10.

A tap selecting section 231, receiving the frequency fluctuation Δfwhich represents the amount of jitter detected by the jitter detectingcircuit 220, compares it with a predetermined reference voltage (such as−B, −A, 0, A, B). The frequency fluctuation Δf is replaced by a tapselection signal according to the large and small relationships with thereference voltage, and is supplied to a tap switching section 232. Onthe other hand, the signal passing through the digital-analog conversionis supplied to a first end of the series connection of a plurality ofdelay elements 233, and is provided with the delay as follows. When thenumber of the delay elements 233 connected in series is assumed to befour as shown in FIG. 10 (actually the number is great), the delayoutput can be pulled out of each of the four output terminals of thedelay elements. Each output terminal of the delay elements 233 isconnected to a corresponding tap of the tap switching section 232. Eachtap is selected in response to the tap selection signal, and the signalobtained from the tap selected is the signal resulting from providingthe delay corresponding to the frequency fluctuation Δf to the signalpassing through the digital-analog conversion. Thus, the signal passingthrough the digital-analog conversion has been subjected to the phaseshift processing according to the amount of jitter detected.

Next, characteristics of the sampling operation using the digital-analogconversion apparatus of FIG. 9 will be described.

The signal passing through the digital-analog conversion by thedigital-analog converter 240 according to an ideal sampling clockwithout the jitter component has a stepwise analog waveform as shown inFIG. 11, which is sampled at regular intervals without phasefluctuations. In practice, however, the sampling clock delivered fromthe oscillator 210 is apt to include the jitter component. Accordingly,the signal passing through the digital-analog conversion by the samplingclock including the jitter component becomes as illustrated in FIG. 12.More specifically, since the sampling clock varies its sampling phasesfrom its original value because of the jitter, the stepwise analogwaveform obtained by the digital-analog conversion has a distortedwaveform as compared with the ideal waveform without jitter as shown inFIG. 11. In contrast with this, when the digital-analog conversionapparatus in accordance with the present invention is applied, thesignal passing through the digital-analog conversion becomes a stepwiseanalog waveform whose phase fluctuations are compensated as shown inFIG. 13. The compensation is carried out by the jitter applying circuit230 by adding the delay based on the amount of jitter to the signalpassing through the digital-analog conversion. As a result, the analogvalues (signal passing through filtering in FIG. 13) finally obtained bythe digital-analog conversion have substantially the same period as inthe ideal state without jitter.

As described above, the present embodiment 3 is configured in such amanner that the jitter detecting circuit detects the amount of jitterincluded in the sampling clock, and the jitter applying circuit providesthe delay based on the amount of jitter detected to the signal passingthrough the digital-analog conversion, thereby compensating for thephase shift resulting from the digital-analog conversion due to thejitter of the sampling clock. As a result, the present embodiment 3 canobtain the analog values at substantially the same period as in theideal state without jitter, thereby being able to implement the highlyaccurate digital-analog conversion.

EMBODIMENT 4

The foregoing embodiment 3 is described by way of example ofoversampling in which the frequency band of the signal passing throughthe digital-analog conversion is equal to or less than half thefrequency of the sampling clock. The present embodiment 4 will bedescribed by way of example of the digital-analog conversion apparatusthat carries out undersampling.

Assume here that the frequency of the sampling clock is fs, the minimumfrequency in the aliasing components of the signal passing through thedigital-analog conversion is f′ min, and the maximum frequency is f′max. When aliasing components appearing in the frequency band satisfyingthe conditionsN×fs≦f′min and f′max≦(N+1)×fs  (2)the band from f′ min to f′ max shifts at the frequency N times thejitter of the sampling clock. FIG. 14 is a block diagram showing aconfiguration of the digital-analog conversion apparatus when carryingout such undersampling. It extracts and uses the aliasing components ofharmonics of the output of the digital-analog converter with a filter orthe like.

In FIG. 14, the same components as those of FIG. 9 are designated by thesame reference numerals and their description will be omitted inprinciple. The configuration includes in addition to that of FIG. 9 ajitter multiplication circuit 250 and a variable DC voltage source 255.

The jitter multiplication circuit 250 is a circuit for multiplying theamount of jitter, the output of the jitter detecting circuit 220, by N.The value N is made variable by a control signal output from thevariable DC voltage source 255. The amount of jitter multiplied by thejitter multiplication circuit 250 is supplied to the jitter applyingcircuit 230. The jitter applying circuit 230 adds to the signal passingthrough the digital-analog conversion a delay based on N times theamount of jitter, thereby compensating for the phase fluctuations due tojitter.

As described above, the embodiment 4 is configured in such a manner thatthe jitter amount multiplication circuit multiplies the amount of jitterdetected, and the jitter applying circuit provides the signal after thedigital-analog conversion with the delay based on the amount of jittermultiplied, thereby compensating for the phase shift caused by thejitter of the sampling clock. As a result, even in the case ofundersampling, the present embodiment 4 can also obtain the analogvalues at substantially the same period as in the ideal state withoutjitter, thereby being able to implement the highly accuratedigital-analog conversion.

INDUSTRIAL APPLICABILITY

As described above, the analog-digital conversion apparatus and thedigital-analog conversion apparatus in accordance with the presentinvention can prevent the deterioration of the conversion accuracy dueto the sampling clock including the jitter component. Accordingly, theyare effectively applicable to the analog-digital conversion ordigital-analog conversion of such devices as radio communicationsapparatuses and measurement instruments.

1. An analog-digital conversion apparatus comprising: an analog-digitalconverter for carrying out analog-digital conversion of an analogsignal; an oscillator for generating a sampling clock used for samplingthe analog signal by said analog-digital converter; a jitter detectingcircuit for detecting an amount of jitter included in the sampling clockgenerated; and a jitter applying circuit for providing the analog signalto be subjected to the analog-digital conversion with a delay based onthe amount of jitter detected to prevent phase shift of the sampling dueto jitter of the sampling clock in said analog-digital converter.
 2. Theanalog-digital conversion apparatus according to claim 1, furthercomprising a delay element for providing the sampling clock input tosaid analog-digital converter with a delay equal to a processing time ofsaid jitter detecting circuit and said jitter applying circuit.
 3. Theanalog-digital conversion apparatus according to claim 1, furthercomprising a jitter amount multiplication circuit for multiplying theamount of jitter detected by said jitter detecting circuit, wherein saidjitter applying circuit provides the analog signal to be subjected tothe analog-digital conversion with a delay based on the amount of jittermultiplied.
 4. The analog-digital conversion apparatus according toclaim 3, wherein said jitter amount multiplication circuit makes anamount of multiplication variable by a control signal.
 5. Theanalog-digital conversion apparatus according to claim 3, furthercomprising a delay element for providing the sampling clock input tosaid analog-digital converter with a delay equal to a processing time ofsaid jitter detecting circuit, said jitter applying circuit and saidjitter amount multiplication circuit.
 6. A digital-analog conversionapparatus comprising: a digital-analog converter for carrying outdigital-analog conversion of a digital signal; an oscillator forgenerating a sampling clock used for establishing synchronization insaid digital-analog converter; a jitter detecting circuit for detectingan amount of jitter included in the sampling clock generated; and ajitter applying circuit for providing the signal after thedigital-analog conversion with a delay based on the amount of jitterdetected to compensate for phase shift occurring in the signal after thedigital-analog conversion due to jitter of the sampling clock.
 7. Thedigital-analog conversion apparatus according to claim 6, furthercomprising a delay element for providing the signal after thedigital-analog conversion to be input to said jitter applying circuitwith a delay equal to a processing time of said jitter detecting circuitand said jitter applying circuit.
 8. The digital-analog conversionapparatus according to claim 6, further comprising a jitter amountmultiplication circuit for multiplying the amount of jitter detected bysaid jitter detecting circuit, wherein said jitter applying circuitprovides the signal after the digital-analog conversion with a delaybased on the amount of jitter multiplied.
 9. The digital-analogconversion apparatus according to claim 8, wherein said jitter amountmultiplication circuit makes an amount of multiplication variable by acontrol signal.
 10. The digital-analog conversion apparatus according toclaim 8, further comprising a delay element for providing the signalafter the digital-analog conversion to be input to said jitter applyingcircuit with a delay equal to a processing time of said jitter detectingcircuit, said jitter amount multiplication circuit and said jitterapplying circuit.